The invention relates to a circuit arrangement for a memory cell of a D/A converter, and in particular to a memory cell in which an analog current is switched by means of a stored digital signal.
A widely used kind of D/A converter comprises a number of stages to which currents with binarily graded values are supplied by current generators, and this supplied current is passed on to an output or derived therefrom, or passed on to another output in dependence on a binary value stored in the relevant stage each time. An example of such a D/A converter is shown in FIG. 1 and comprises a number of stages L1, L2 . . . Ln, as well as a number of current generators CG1, CG2 . . . CGn. Each current generator comprises a series arrangement of a resistor and a transistor, one end of the resistor being connected to a line 10 for a reference voltage, i.e. in general ground, while the bases of all transistors are connected to a line 11 for receiving an auxiliary voltage. The resistors are so dimensioned that a current will flow in the collector of the transistor of a given current generator which has double the value of the current flowing in the preceding current generator. These currents are supplied to a current input 12 of a relevant stage L1, L2 . . . Ln, which delivers this current to a current output 20 in dependence on a digital value stored in this stage, all current outputs being interconnected, and thus supplying a summed current Is. The binary values stored in the individual stages are supplied in advance via a data input 16 and written into the stages by means of a signal on a control line 14.
If such a D/A converter is to be integrated together with further analog circuits in a semiconductor, a manufacturing process will often be used for this in which only analog circuits can be usefully manufactured, but no digital circuits, so that digital circuits are to be realized by analog means. This is true in particular when the integration technology used does not allow the manufacture of circuits in accordance with the IIL-technology.
FIG. 2 shows a circuit arrangement for a memory cell of a D/A converter corresponding to one of the stages L1, L2, etc. in FIG. 1, constructed in a conventional analog technology. The analog current supplied to a current input 12 is conducted to the emitters of two transistors Q11 ad Q12 whose bases are controlled with different voltages so that the supplied current is either fully delivered through the output 20 or is removed through a line 18 connected to the operating voltage. The transistors Q11 and Q12 thus act as a switch which is controlled by a flipflop formed by transistors Q1 and Q2, which are cross-coupled, i.e. the base of each of these transistors is connected to the collector of the other transistor via a respective resistor R1, R2.
The transistors Q11 and Q12 forming the switch are controlled by the transistors Q3 and Q4, respectively, connected in parallel to the transistors Q1 and Q2 via the respective resistors R3 and R4, and by the resistors R11 and R12 connected to the collectors of Q3 and Q4. Resistors are always necessary in the base lines in the case of parallel-connected base connections for reasons of current division. The flipflop is supplied with current via the resistors R14 and R15 which are connected to the line 18 for the supply voltage. Transistors Q5 and Q6, by means of which the binary value can be set in the flipflop, are connected in parallel to the transistors Q1 and Q2 of the flipflop. For this purpose, the base of the transistor Q5 is connected via a resistor R5 to the collectors of two further transistors Q7 and Q10 which are connected via a further resistor R9 to a further transistor Q9 and via a resistor R16 to the line 18. The collector of the transistor Q9 is connected via a resistor R15 to the line 18 and also to the base of the transistor Q6 and the collector of a transistor Q8. The bases of the transistors Q7 and Q8 are connected to the control input 14 via respective resistors R7 and R8, and the transistor Q10 is connected to the data input 16 via a resistor R10. As long as the control input 14 is at a high potential, the transistors Q7 and Q8 are conducting, and the transistors Q5 and Q6 are accordingly cut off, so that the state of the flipflop is not affected. When the control input 14 is at a low potential, the transistors Q7 and Q8 are cut off, and the transistor Q9 or Q10 is cut off in dependence on the signal at the data input 16, and the transistor Q5 or Q6 is accordingly conducting, with the result that the flipflop is set for the binary value applied to the data input 16.
It is a disadvantage of this circuit that many components are required and that the integration requires much surface space, because the transistors must be realized in separate islands. Furthermore, the delay times in this circuit are not ideal because two transistor delay periods, i.e. those of the transistors Q7 and Q5 or Q8 and Q6, are required for activating the control input 14 each time before the state of the flipflop with the transistors Q1 and Q2 is changed. It is also a disadvantage that all supply currents in the circuit remain unchanged during the period in which the control input is at a high potential and accordingly no write action takes place, so that the current consumption is comparatively high.